RTL Design and Verification
Learn with ABHYASA
9 modules
English
Access for 30 days
"Master the art of VLSI design and verification for groundbreaking innovations in the world of technology!"
Overview
This course provides a comprehensive overview of VLSI Design and Verification. Students will gain hands-on experience in developing, testing, and debugging VLSI circuits using industry-standard tools and techniques.
Key Highlights
VLSI design fundamentals
Verification methodologies
Hands-on project work
What you will learn
Deep dive into VLSI design
Understand the fundamentals of VLSI design process and tools
Verification techniques
Learn various verification methodologies and practices
Hands-on projects
Apply learned concepts through practical VLSI design projects
Modules
Verilog HDL
10 attachments • 9 hrs
Introduction to Verilog HDL
Basics of Verilog
Abstraction Levels
Datatypes
Logical Operators
Verilog Testbench
Verilog Testbench - 2
Verilog Testbench & It's events
Assignment - 1
Assignment - 2
Advanced Verilog
5 attachments • 5 hrs
Behavioral Modeling - 1
Behavioral Modeling - 2
Blocking & Non-Blocking Assignments
Time Scale Precision
Verilog HDL
Verilog Practical Sessions
4 attachments • 4 hrs
Session - 1
Session -2 ( Coding on Sequential Circuits)
Session - 3
Session - 4
System Verilog ( HVL )
14 attachments • 13 hrs
Introduction to SV
SV Testbench - 1
Data Types - 1
Data Types - 2
Arrays - 1
Arrays - 2
SV_ASSIGNMENT - 1
Array Manipulations - 1
Array Manipulations - 2
Procedural Statements - 1
Procedural Statements - 2
Tasks & Functions - 1
Tasks & Functions - 2
Process - 1
Universal Verification Methodology (UVM )
6 attachments • 4 hrs
Introduction to UVM - Testbench
Handling Mechanism
UVM Factory
Introduction to AXI Protocol
AXI Protocol - UVM Scoreboard
Project Insights
OOPs
20 attachments • 16 hrs
Basic OOPs
Oops class constructor
This keyword,class assignment
Class assignment
Parameterized class and class inheritance
Introduction to Randomizatoin
Randomization - 2
Constraints - 1
Constraints - 2
Constraints - 3
Constraints - 4
Semaphore
Mailbox
Functional Coverage
SV Testbench - Project01
SV Testbench - Project02
SV Testbench - Practice
Verification Model - 1
Verification Model - 2
Verification Model - 3
LINUX
3 attachments • 2 hrs
Linux-1
Linux-2
Assignment
TCL
3 attachments • 2 hrs
TCL - 1
TCL - 2
TCL - 3
VIVA Sessions
1 attachment
VIVA Session01
FAQs
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Can I interact with the instructor during the course?
Absolutely! we are committed to providing an engaging and interactive learning experience. You will have opportunities to interact with them through our community. Take full advantage to enhance your understanding and gain insights directly from the expert.
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